555 timer IC

[큰나무]

The 555 timer IC is an integrated circuit (chip) used in a variety of timer, pulse generation, and oscillator applications.

The 555 can be used to provide time delays, as an oscillator, and as a flip-flop element.

Derivatives provide up to four timing circuits in one package.

Introduced in 1971 by American company Signetics, the 555 is still in widespread use due to its low price, ease of use, and stability.

It is now made by many companies in the original bipolar and also in low-power CMOS types.

As of 2003^[update], it was estimated that 1 billion units are manufactured every year.

Astable

In astable mode, the 555 timer puts out a continuous stream of rectangular pulses having a specified frequency.

Resistor R₁ is connected between V_CC and the discharge pin (pin 7) and another resistor (R₂) is connected between the discharge pin (pin 7), and the trigger (pin 2) and threshold (pin 6) pins that share a common node.

Hence the capacitor is charged through R₁ and R₂, and discharged only through R₂, since pin 7 has low impedance to ground during output low intervals of the cycle, therefore discharging the capacitor.

In the astable mode, the frequency of the pulse stream depends on the values of R₁, R₂ and C:

The high time from each pulse is given by:

and the low time from each pulse is given by:

where R₁ and R₂ are the values of the resistors in ohms and C is the value of the capacitor in farads.

The power capability of R₁ must be greater than .

Particularly with bipolar 555s, low values of must be avoided so that the output stays saturated near zero volts during discharge, as assumed by the above equation.

Otherwise the output low time will be greater than calculated above.

The first cycle will take appreciably longer than the calculated time, as the capacitor must charge from 0V to 2/3 of V_CC from power-up, but only from 1/3 of V_CC to 2/3 of V_CC on subsequent cycles.

To have an output high time shorter than the low time (i.e., a duty cycle less than 50%) a small diode (that is fast enough for the application) can be placed in parallel with R₂, with the cathode on the capacitor side.

This bypasses R₂ during the high part of the cycle so that the high interval depends only on R₁ and C, with an adjustment based the voltage drop across the diode.

The voltage drop across the diode slows charging on the capacitor so that the high time is a longer than the expected and often-cited ln(2)*R₁C = 0.693 R₁C.

The low time will be the same as above, 0.693 R₁C. With the bypass diode, the high time is

where V_diode is when the diode's "on" current is 1/2 of V_cc/R₁ which can be determined from its datasheet or by testing.

As an extreme example, when V_cc= 5 and V_diode= 0.7, high time = 1.00 R₁C which is 45% longer than the "expected" 0.693 R₁C.

At the other extreme, when V_cc= 15 and V_diode= 0.3, the high time = 0.725 R₁C which is closer to the expected 0.693 R₁C.

The equation reduces to the expected 0.693 R₁C if V_diode= 0.

The operation of RESET in this mode is not well-defined.

Some manufacturers' parts will hold the output state to what it was when RESET is taken low, others will send the output either high or low.

The astable configuration, with two resistors, cannot produce a 50% duty cycle.

To produce a 50% duty cycle, eliminate R1, disconnect pin 7 and connect the supply end of R2 to pin 3, the output pin.

This circuit is similar to using an inverter gate as an oscillator, but with fewer components than the astable configuration, and a much higher power output than a TTL or CMOS gate.

The duty cycle for either the 555 or inverter-gate timer will not be precisely 50% due to the fact the timing network is supplied from the devices output pin, which has different internal resistances depending on whether it is in the high or low state (high side drivers tend to be more resistive).