d-flipflop synchronizing clk at 5hz

[정다훈]

1. modeling

# RTL File

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

module Sync_dff_rising(clk_in,out_q);     input clk_in;     output out_q;          wire clck_5hz;     wire out_q;          clck_5hz(clk_in,clck_5hz);     dff_rising_edge utClk5hz(clck_5hz,out_q); endmodule   module dff_rising_edge(clk_in,q);     input clk_in;     input sel;     output q;          reg sel;     reg q;          always @(posedge clk_in) begin         q <= sel;     end endmodule          module clck_5hz(clk_in,clk_out);   input clk_in;    output clk_out;      reg clk_out;   reg [15:0] cnt;      initial begin     clk_out = 1'b0;     cnt = 16'd0;   end      always @ (posedge clk_out) begin     if(cnt == 16'd49) begin         clk_out = ~clk_out;         cnt <= 16'd0;     end         else         cnt <= cnt + 1'd1;    end endmodule Colored by Color Scripter

cs

2. Test

# Test Bench File

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

module tb_Sync_dff_rising;    reg clk_in;    wire out_q;      Sync_dff_rising dut(     .clck_5hz(clk_in),     .out_q(out_q));        initial begin     clk_in = 1'b0;     #10000 $stop;   end      always #20 clk_in <= ~clk_in;    endmodule

cs

3. ModelSim