VHDL to Verilog convert 요청

[밝은미소]

안녕하세요~~

또 간만에... 글 올립니다.

UART 통신 하기 위한 vhdl 코드 인데요~

아래 코드 중에 verilog로 어떻게 converting 해야 하는지 몰라서.. 요청 드립니다.

빨간색 부분이요~~^^; 추가적으로..  vhdl에서 ( :=  )는 무슨 의미인지요?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity uart3_rx_tx_unit is
 port (  clk50m   : in  STD_LOGIC;
    sw11    : in  STD_LOGIC;
    
    rxd         : in  std_logic;    -- RS232 receiver line
    txd         : out std_logic;    -- RS232 transmitter line    
    
      dip_switch : in  std_logic_vector(2 downto 0);
      led   : out std_logic_vector(7 downto 0);   
    
    lcd_en   : out std_logic;
    lcd_rs  : out std_logic;
    lcd_rw  : out std_logic;
    lcd_data  : out std_logic_vector(7 downto 0));   
end uart3_rx_tx_unit;

architecture Behavioral of uart3_rx_tx_unit is
component bufg
 port( i : in std_logic;
   o  : out std_logic);
end component;

component CLCD
 port ( clk_1khz_bufg : IN std_logic;
    reset    : IN std_logic;
    
    rx_clk_dit0  : IN std_logic_VECTOR(3 downto 0);
    rx_clk_dit1  : IN std_logic_VECTOR(3 downto 0);
    rx_clk_dit2  : IN std_logic_VECTOR(3 downto 0);
    rx_clk_dit3  : IN std_logic_VECTOR(3 downto 0);
    rx_clk_dit4  : IN std_logic_VECTOR(3 downto 0);
    rx_clk_dit5  : IN std_logic_VECTOR(3 downto 0);    

    tx_clk_dit0  : IN std_logic_VECTOR(3 downto 0);
    tx_clk_dit1  : IN std_logic_VECTOR(3 downto 0);
    tx_clk_dit2  : IN std_logic_VECTOR(3 downto 0);
    tx_clk_dit3  : IN std_logic_VECTOR(3 downto 0);
    tx_clk_dit4  : IN std_logic_VECTOR(3 downto 0);
    tx_clk_dit5  : IN std_logic_VECTOR(3 downto 0);       
    
    rx_data   : IN std_logic_VECTOR(7 downto 0);       
    
    lcd_en   : OUT std_logic;
    lcd_rs   : OUT std_logic;
    lcd_rw   : OUT std_logic;    
    lcd_data   : OUT std_logic_VECTOR(7 downto 0));
end component;

component uart
 port ( reset      : IN std_logic;
    baudrate_rx_clk_bufg : IN std_logic;
    baudrate_tx_clk_bufg : IN std_logic;
    rxd      : IN std_logic;
    txd      : out std_logic;
    
    rx_data     : out std_logic_VECTOR(7 downto 0));    
end component;

signal reset     : std_logic;

signal cnt_1khz    : integer range 0 to 25000;
signal clk_1khz     : std_logic;
signal clk_1khz_bufg   : std_logic;

signal temp      : std_logic_vector(2 downto 0) := (others => '0');
                     -- dip_switch :   bps  : standard :     display    :
constant bps2400    : integer range 0 to 3000 := 2603;  --    000     :   2400 :     9600 : 2604 ->   9597 : 2603 ->   9601 :
constant bps9600    : integer range 0 to 3000 := 650; --    001     :   9600 :    38400 :  650 ->  38402 :  650 ->  38402 :
constant bps19200    : integer range 0 to 3000 := 325; --    010     :  19200 :    76800 :  325 ->  76687 :  324 ->  76923 :
constant bps38400    : integer range 0 to 3000 := 162; --    011     :  38400 :   153600 :  162 -> 153374 :  161 -> 154321 :
constant bps57600    : integer range 0 to 3000 := 108; --    100     :  57600 :   230400 :  108 -> 229358 :  107 -> 231482 :
constant bps115200   : integer range 0 to 3000 := 54;  --    1XX     : 115200 :   460800 :   54 -> 454545 :   53 -> 462963 :

signal cnt_detect    : integer range 0 to 51000000;
signal detect_flag   : std_logic_vector(1 downto 0) := (others => '0');

signal adj_value    : integer range 0 to 3000;
signal baud_rate_cnt   : integer range 0 to 3000;
signal baudrate_rx_clk  : std_logic; 
signal baudrate_rx_clk_bufg: std_logic;

signal tx_cnt     : std_logic_vector(1 downto 0) := (others => '0');
signal baudrate_tx_clk  : std_logic; 
signal baudrate_tx_clk_bufg: std_logic;

signal d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11  : integer range 0 to 15;
signal rx_clk_dit0,rx_clk_dit1,rx_clk_dit2,rx_clk_dit3,rx_clk_dit4,rx_clk_dit5 : std_logic_vector(3 downto 0) := (others => '0');
signal tx_clk_dit0,tx_clk_dit1,tx_clk_dit2,tx_clk_dit3,tx_clk_dit4,tx_clk_dit5 : std_logic_vector(3 downto 0) := (others => '0');

signal rx_data  : Std_Logic_Vector(7 downto 0); -- receive register 
signal tx_step  : Std_Logic_Vector(3 downto 0) := (others => '0');

begin
 bufg0 : bufg
 port map(
  i => clk_1khz,
  o => clk_1khz_bufg);  
  
 bufg1 : bufg
 port map(
  i => baudrate_rx_clk,
  o => baudrate_rx_clk_bufg);
  
 bufg2 : bufg
 port map(
  i => baudrate_tx_clk,
  o => baudrate_tx_clk_bufg); 

 display1 : CLCD port map(
    clk_1khz_bufg => clk_1khz_bufg,
    reset => reset,
    
    rx_clk_dit0 => rx_clk_dit0,
    rx_clk_dit1 => rx_clk_dit1,
    rx_clk_dit2 => rx_clk_dit2,
    rx_clk_dit3 => rx_clk_dit3,
    rx_clk_dit4 => rx_clk_dit4,
    rx_clk_dit5 => rx_clk_dit5,
    
    tx_clk_dit0 => tx_clk_dit0,
    tx_clk_dit1 => tx_clk_dit1,
    tx_clk_dit2 => tx_clk_dit2,
    tx_clk_dit3 => tx_clk_dit3,
    tx_clk_dit4 => tx_clk_dit4,
    tx_clk_dit5 => tx_clk_dit5,
    
    rx_data => rx_data,
    
    lcd_en => lcd_en,
    lcd_rs => lcd_rs,
    lcd_rw => lcd_rw,
    lcd_data => lcd_data); 

 serial : uart port map(
    reset => reset,  
    baudrate_rx_clk_bufg => baudrate_rx_clk_bufg,
    baudrate_tx_clk_bufg => baudrate_tx_clk_bufg,
    rxd => rxd, 
    txd => txd,     
    rx_data => rx_data);
  
 reset <= sw11;  
 baudrate_tx_clk <= tx_cnt(1); 
 led <= rx_data;
 
 process(reset,clk50m)
 begin
  if(reset = '1') then
   cnt_1khz <= 0;   
  elsif rising_edge(clk50m) then
   if(cnt_1khz >= 25000)  then   
    cnt_1khz <= 0;
    clk_1khz <= not clk_1khz;
   else
    cnt_1khz <= cnt_1khz + 1;
   end if;
  end if;
 end process;
 
 process(reset,clk50m)
 begin
  if(reset = '1') then
   cnt_detect <= 0; 
   detect_flag <= "00";
  elsif rising_edge(clk50m) then
   if(cnt_detect >= 50100000)  then
    cnt_detect <= 0;    
   else
    cnt_detect <= cnt_detect + 1;
   end if;
   
   if(cnt_detect <= 50000000)  then
    detect_flag <= "01";
   elsif((cnt_detect > 50000000) and (cnt_detect <= 50050000)) then
    detect_flag <= "10";
   else
    detect_flag <= "00";
   end if;   
  end if;
 end process; 
 
 process(reset,dip_switch)
 begin
  if(reset = '1') then
   adj_value <= bps2400;
  else               
   case dip_switch is         -- : dip switch : rx clock : tx clock :
    when "000" => adj_value <= bps2400;   -- :    000     :    9600  :    2400  : 
    when "001" => adj_value <= bps9600;   -- :    001     :   38400  :    9600  : 
    when "010" => adj_value <= bps19200;  -- :    010     :   76800  :   19200  : 
    when "011" => adj_value <= bps38400;  -- :    011     :  153600  :   38400  : 
    when "100" => adj_value <= bps57600;  -- :    100     :  230400  :   57600  : 
    when others => adj_value <= bps115200;  -- :    1XX     :  460800  :  115200  : 
   end case;            -- : X : don't care
  end if;
 end process;  
 
 process(reset,clk50m)
 begin
  if(reset = '1') then
   baud_rate_cnt <= 0;   
  elsif rising_edge(clk50m) then  
   if(baud_rate_cnt >= adj_value)  then   
    baud_rate_cnt <= 0;
    baudrate_rx_clk <= not baudrate_rx_clk;
   else
    baud_rate_cnt <= baud_rate_cnt + 1;
   end if;
  end if;
 end process; 
 
 process(baudrate_rx_clk_bufg,reset)
 begin
  if(reset = '1') then
   tx_cnt <= (others => '0');   
  elsif rising_edge(baudrate_rx_clk_bufg) then
   tx_cnt <= tx_cnt + 1;
  end if;
 end process;
 
 process(baudrate_rx_clk_bufg,detect_flag)
 begin
  if(reset = '1') then
   d0 <= 0;
   d1 <= 0;
   d2 <= 0;
   d3 <= 0;
   d4 <= 0;
   d5 <= 0;   
  elsif rising_edge(baudrate_rx_clk_bufg) then   
   if(detect_flag = "01") then 
    if(d0 = 9) then
     d0 <= 0;
     if(d1 = 9) then
      d1 <= 0;
      if(d2 = 9) then
       d2 <= 0;
       if(d3 = 9) then
        d3 <= 0;
        if(d4 = 9) then
         d4 <= 0;
         if(d5 = 9) then
          d5 <= 0;          
         else
          d5 <= d5 + 1;
         end if;
        else
         d4 <= d4 + 1;
        end if;         
       else
        d3 <= d3 + 1;
       end if;
      else
       d2 <= d2 + 1;
      end if;
     else
      d1 <= d1 + 1;
     end if;
    else
     d0 <= d0 + 1;
    end if;    
   elsif(detect_flag = "10") then 
    rx_clk_dit0 <= conv_std_logic_vector(d0,4);
    rx_clk_dit1 <= conv_std_logic_vector(d1,4);
    rx_clk_dit2 <= conv_std_logic_vector(d2,4);
    rx_clk_dit3 <= conv_std_logic_vector(d3,4);
    rx_clk_dit4 <= conv_std_logic_vector(d4,4);
    rx_clk_dit5 <= conv_std_logic_vector(d5,4);    
   else
    d0 <= 0;
    d1 <= 0;
    d2 <= 0;
    d3 <= 0;
    d4 <= 0;
    d5 <= 0;    
   end if;  
  end if;   
 end process;   
 
 process(baudrate_tx_clk_bufg,detect_flag)
 begin
  if(reset = '1') then
   d6 <= 0;
   d7 <= 0;
   d8 <= 0;
   d9 <= 0;
   d10 <= 0;
   d11 <= 0;   
  elsif rising_edge(baudrate_tx_clk_bufg) then   
   if(detect_flag = "01") then 
    if(d6 = 9) then
     d6 <= 0;
     if(d7 = 9) then
      d7 <= 0;
      if(d8 = 9) then
       d8 <= 0;
       if(d9 = 9) then
        d9 <= 0;
        if(d10 = 9) then
         d10 <= 0;
         if(d11 = 9) then
          d11 <= 0;          
         else
          d11 <= d11 + 1;
         end if;
        else
         d10 <= d10 + 1;
        end if;         
       else
        d9 <= d9 + 1;
       end if;
      else
       d8 <= d8 + 1;
      end if;
     else
      d7 <= d7 + 1;
     end if;
    else
     d6 <= d6 + 1;
    end if;    
   elsif(detect_flag = "10") then 
    tx_clk_dit0 <= conv_std_logic_vector(d6,4);
    tx_clk_dit1 <= conv_std_logic_vector(d7,4);
    tx_clk_dit2 <= conv_std_logic_vector(d8,4);
    tx_clk_dit3 <= conv_std_logic_vector(d9,4);
    tx_clk_dit4 <= conv_std_logic_vector(d10,4);
    tx_clk_dit5 <= conv_std_logic_vector(d11,4);    
   else
    d6 <= 0;
    d7 <= 0;
    d8 <= 0;
    d9 <= 0;
    d10 <= 0;
    d11 <= 0;    
   end if;  
  end if;   
 end process; 
end Behavioral;

[SystemVerilog]

smith chip design책 찾아보시면 변환에대해서 잘나왔습니다~~ :=은 프로세스안에서만 사용되는 변수로 reg형으로 생각하면됩니다

[밝은미소]

아하 그렇군요~~ 감사합니다~~^^

[SystemVerilog]

인스턴스 생성, 벡터신호대입~~~

[SystemVerilog]

constant는 parameter에 대응됩니다

[SystemVerilog]

형변환함수는 크기를 잘고려해서 대입시키면됩니다

[밝은미소]

네네~~
컨버팅 작업해봐야겠어요~^^
특히 conv_std_logic_vector(d6,4) <= 이부분 때문에 어떻게 verilog로 표현하나했는데... 상세한 설명 감사드립니다.

[SystemVerilog]

tx_clk_dit0 <= conv_std_logic_vector(d6,4);를 바꾸면
tx_clk_dit0[3:0] = 4'd6 ;

[SystemVerilog]

가산기가 너무 마니들어갔네요

[밝은미소]

그런가요?? 전 조금씩 비교하면서 컨버팅하고 있었네요~~^^