Re: Re: Re: 계수기

[견우]

module COUNTER
 #(parameter N=32)
 (
 (* IOB="true" *)  input refclk,
  (* IOB="true" *) input rst_n,
  (* IOB="true" *) output co,
  (* IOB="true" *) output co_e,
  (* IOB="true" *) output co_o,
  (* IOB="true" *) output [N-1:0] q1,q2 ,q3,q4,
    (* IOB="true" *) output reg [N-1:0] q
  );

//wire [31:0] out1,out2;
wire co_e1,co_o1;
wire co_e2;  //co_e3,co_e4;
wire co_o2;  // co_o3,co_o4;
wire clk,clk2;
wire reset = ~rst_n & locked;

  clk_wiz_0  U00
  (
  // Clock out ports  
  .clk_out1(clk1),    //CLK1666.666M
  .clk_out2(clk2),   //CLK333.3333M
  .clk_out3(clk3),   //CLK666.6666M
  // Status and control signals               
  .reset(reset), 
  .locked(locked),
 // Clock in ports
  .clk_in1(refclk)
  );
(* dont_touch ="yes" *) reg [N-1:0] tq1[3:0];
(* dont_touch ="yes" *) reg [N-1:0] tq2[3:0];
(* dont_touch ="yes" *) reg [N-1:0] tq3[3:0];
(* dont_touch ="yes" *) reg [N-1:0] tq4[3:0];
(* dont_touch ="yes" *) reg [N-1:0] tqr1;
(* dont_touch ="yes" *) wire [N-1:0] tqo,tqo1;
reg t1,t0;

always @(posedge clk3)
 begin

 if(rst_n==1'b1)
  begin
  tq1[0]<=q1;
  tq1[1]<=tq1[0];
  tq1[2]<=tq1[1];
  tq1[3]<=tq1[2];
  tq2[0]<=q2;
  tq2[1]<=tq2[0];
  tq2[2]<=tq2[1];
  tq2[3]<=tq2[2];
  tq3[0]<=q3;
  tq3[1]<=tq3[0];
  tq3[2]<=tq3[1];
  tq3[3]<=tq3[2];
  tq4[0]<=q4;
  tq4[1]<=tq4[0];
  tq4[2]<=tq4[1];
  tq4[3]<=tq4[2];
/*  tq2[3:0]<={tq2[2:0],q2};
  tq3[3:0]<={tq3[2:0],q3};
  tq4[3:0]<={tq4[2:0],q4};
*/ 
 //tq2<=q2;
  //tq3<=q3;
  //tq4<=q4;
  tqr1<=tqo;
 // q[31:2]<=tqr1[31:2];
 // q[0]<=tqr1[0];
 // t1<=(t0==1'b1)?~tqr1[1]:1'b0;
 // q[1]<=t1;
  
  q[31:0]<=tqr1;
   end
  else
   begin
  tq1[0]<=q1;
  tq1[1]<=tq1[0];
  tq1[2]<=tq1[1];
  tq1[3]<=tq1[2];
  tq2[0]<=q2;
  tq2[1]<=tq2[0];
  tq2[2]<=tq2[1];
  tq2[3]<=tq2[2];
  tq3[0]<=q3;
  tq3[1]<=tq3[0];
  tq3[2]<=tq3[1];
  tq3[3]<=tq3[2];
  tq4[0]<=q4;
  tq4[1]<=tq4[0];
  tq4[2]<=tq4[1];
  tq4[3]<=tq4[2];
  tqr1<=tqo;
   end
end 

always @(posedge q[0] or negedge rst_n)
begin
if(rst_n==1'b0)
t0<=1'b0;
else
t0<=1'b1;
end

generate
  genvar i;
    for(i=0; i<N; i=i+1)
      begin:genI
        LUT6 #(.INIT(64'b1111_1111_0000_0000__1111_0000_1111_0000__1100_1100_1100_1100__1010_1010_1010_1010)) L00 (.O(tqo1[i]),.I0(tq1[3][i]),.I1(tq2[3][i]),.I2(tq3[3][i]),.I3(tq4[3][i]),.I4(clk2),.I5(clk1));
LUT1 #(.INIT(2'b10)) L01 (.O(tqo[i]),.I0(tqo1[i]));
      end
 endgenerate

LUT36_p U0
 (
   .clk(clk1),
   .rst_n(rst_n),
   .i({q1[31:2],2'b11}),
   .o(co_e2),
   .o1(co)
   );

LUT36_p U1
 (
   .clk(clk1),
   .rst_n(rst_n),
   .i({q2[31:2],2'b11}),
   .o(co_o2),
   .o1()
   );


/*
assign q1[1:0]=2'b00;
assign q2[1:0]=2'b01;
assign q3[1:0]=2'b10;
assign q4[1:0]=2'b11;
*/

assign q1[1:0]=2'b11;
assign q2[1:0]=2'b10;
assign q3[1:0]=2'b01;
assign q4[1:0]=2'b00;
assign co_e = co_e2;
assign co_o = co_o2;

COUNTER10_e  CNT1 (.clk(clk1)  ,.rst_n(rst_n),.en(1'b1),.q(q1[11:2])  ,.co(co_e1));
COUNTER10_e1 CNT2 (.clk(clk1),.rst_n(rst_n),.en(co_e1),.q(q1[21:12]));
COUNTER10_e1 CNT3 (.clk(clk1),.rst_n(rst_n),.en(co_e2),.q(q1[31:22]));

COUNTER10_e  CNT4 (.clk(clk1)  ,.rst_n(rst_n),.en(1'b1),.q(q2[11:2]) ,.co(co_o1));
COUNTER10_e1 CNT5 (.clk(clk1),.rst_n(rst_n),.en(co_o1),.q(q2[21:12]));
COUNTER10_e1 CNT6 (.clk(clk1),.rst_n(rst_n),.en(co_o2),.q(q2[31:22])); 

COUNTER10_e  CNT7 (.clk(clk1)  ,.rst_n(rst_n),.en(1'b1),.q(q3[11:2])  ,.co(co_e11));
COUNTER10_e1 CNT8 (.clk(clk1),.rst_n(rst_n),.en(co_e11),.q(q3[21:12]));
COUNTER10_e1 CNT9 (.clk(clk1),.rst_n(rst_n),.en(co_e12),.q(q3[31:22]));

COUNTER10_e  CNT10 (.clk(clk1)  ,.rst_n(rst_n),.en(1'b1),.q(q4[11:2]) ,.co(co_o11));
COUNTER10_e1 CNT11 (.clk(clk1),.rst_n(rst_n),.en(co_o11),.q(q4[21:12]));
COUNTER10_e1 CNT12 (.clk(clk1),.rst_n(rst_n),.en(co_o12),.q(q4[31:22]));

endmodule

module LUT36_p
 (
   input clk,
   input rst_n,
   input  [31:0] i,
   output reg o,
   output reg o1
   );
wire w0,w1,w2,w3,w4,w5,w6,w60,w30;


/*
LUT6 #(.INIT(64'h8000_0000_0000_0000) L0 (.O(w0),.I0(i[0]),.I1(i[1]),.I2(i[2]),.I3(i[3]),.I4(i[4]),.I5(i[5]));
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L1 (.O(w1),.I0(i[6]),.I1(i[7]),.I2(i[8]),.I3(i[9]),.I4(i[10]),.I5(i[11]));
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L2 (.O(w2),.I0(i[12]),.I1(i[13]),.I2(i[14]),.I3(i[15]),.I4(i[16]),.I5(i[17]));
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L3 (.O(w3),.I0(i[18]),.I1(i[19]),.I2(i[20]),.I3(i[21]),.I4(i[22]),.I5(i[23]));
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L4 (.O(w4),.I0(i[24]),.I1(i[25]),.I2(i[26]),.I3(i[27]),.I4(i[28]),.I5(i[29]));
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L5 (.O(w5),.I0(i[30]),.I1(i[31]),.I2(i[32]),.I3(i[33]),.I4(i[34]),.I5(i[35]));
*/
LUT6 #(.INIT(64'h0800_0000_0000_0000)) L0 (.O(w0),.I0(i[0]),.I1(i[1]),.I2(i[2]),.I3(i[3]),.I4(i[4]),.I5(i[5]));
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L1 (.O(w1),.I0(i[6]),.I1(i[7]),.I2(i[8]),.I3(i[9]),.I4(i[10]),.I5(i[11]));
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L2 (.O(w2),.I0(i[12]),.I1(i[13]),.I2(i[14]),.I3(i[15]),.I4(i[16]),.I5(i[17]));
LUT4 #(.INIT(16'h8000)) L3 (.O(w3),.I0(i[18]),.I1(i[19]),.I2(i[20]),.I3(i[21]));
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L30 (.O(w30),.I0(i[18]),.I1(i[19]),.I2(i[20]),.I3(i[21]),.I4(i[22]),.I5(i[23]));
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L4 (.O(w4),.I0(i[24]),.I1(i[25]),.I2(i[26]),.I3(i[27]),.I4(i[28]),.I5(i[29]));
LUT2 #(.INIT(4'h4))                     L5 (.O(w5),.I0(i[30]),.I1(i[31]));
// LUT6 #(.INIT(64'h8000_0000_0000_0000)) L4 (.O(w4),.I0(i[24]),.I1(i[25]),.I2(i[26]),.I3(i[27]),.I4(i[28]),.I5(i[29]));
// LUT2 #(.INIT(4'h1)) L5 (.O(w5),.I0(i[30]),.I1(i[31]));

/*
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L0 (.O(w0),.I0(i[0]),.I1(i[1]),.I2(i[2]),.I3(i[3]),.I4(i[4]),.I5(i[5]));
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L1 (.O(w1),.I0(i[6]),.I1(i[7]),.I2(i[8]),.I3(i[9]),.I4(i[10]),.I5(i[11]));
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L2 (.O(w2),.I0(i[12]),.I1(i[13]),.I2(i[14]),.I3(i[15]),.I4(i[16]),.I5(i[17]));
LUT3 #(.INIT(08'h80)) L3 (.O(w3),.I0(i[18]),.I1(i[19]),.I2(i[20]));
*/
/*
LUT6 #(.INIT(64'h2000_0000_0000_0000)) L0 (.O(w0),.I0(i[0]),.I1(i[1]),.I2(i[2]),.I3(i[3]),.I4(i[4]),.I5(i[5]));
LUT6 #(.INIT(64'h0000_0000_0000_0001)) L1 (.O(w1),.I0(i[6]),.I1(i[7]),.I2(i[8]),.I3(i[9]),.I4(i[10]),.I5(i[11]));
LUT6 #(.INIT(64'h0000_0000_0000_0001)) L2 (.O(w2),.I0(i[12]),.I1(i[13]),.I2(i[14]),.I3(i[15]),.I4(i[16]),.I5(i[17]));
LUT3 #(.INIT(08'h01)) L3 (.O(w3),.I0(i[18]),.I1(i[19]),.I2(i[20]));
*/
reg r0,r1,r2,r3,r4,r5,r30;

always @(posedge clk)
  begin
   if(rst_n==1'b0)
    begin
      r0<=1'b0;
      r1<=1'b0;
      r2<=1'b0;
      r3<=1'b0;
      r4<=1'b0;
      r5<=1'b0;
      o<=1'b0;
      o1<=1'b0;
    end
   else
    begin
      r0<=w0;
      r1<=w1;
      r2<=w2;
      r3<=w3;
      r30 <= w30;
      r4<=w4;
      r5<=w5;
      o <=w6;
      o1 <=w60;


    end
  end

// LUT6 #(.INIT(64'h1000_0000)) L6 (.O(w6),.I0(r0),.I1(r1),.I2(r2),.I3(r3),.I4(r4),.I5(r5));
LUT4 #(.INIT(16'h8000)) L6 (.O(w6),.I0(r0),.I1(r1),.I2(r2),.I3(r3));
LUT6 #(.INIT(64'h1000_0000)) L7 (.O(w60),.I0(r0),.I1(r1),.I2(r2),.I3(r30),.I4(r4),.I5(r5));

endmodule

  
 module COUNTER5_inc2_0
 (
   input clk,rst_n,en,
   output reg [4:0] q
   );
  
 
wire rst=~rst_n;
   
   always @(posedge clk or posedge rst)
    begin
      if(rst==1'b1)
        q<=5'b0;
      else if(en)
        q<=q+1'b1; 
    end
  endmodule
  
  
module COUNTER10_e
  #(parameter ADJ=5'b1_1110)
  (
   input clk,rst_n,en,
   output wire [9:0] q,
   output reg co
   );
//   reg en1,en1_1;


reg co_r;
reg en_1,en_1d;
reg rst_ns;
reg co1;

always @(*)
 begin
   en_1 <= en_1d;
   co <=co1; 
 end

COUNTER5_inc2_0 U0 (.clk(clk),.rst_n(rst_n),.en(en),.q(q[4:0])); 

always @(posedge clk)
 begin
  en_1d<= q[4:0]==5'b1_1110;
  co_r <= q[4:0]==5'b1_1111 && q[9:5]==5'b1_1111; 
  co1  <= q[4:0]==5'b1_1110 && q[9:5]==5'b1_1111; 
  rst_ns <= rst_n & ~co_r;
 end
 
 COUNTER5 U1 (.clk(clk),.rst_n(rst_ns),.en(en_1),.q(q[9:5]));

 endmodule

 
module COUNTER5
 (
   input clk,rst_n,en,
   output reg [4:0] q
   );
   
wire rst=~rst_n;
   
   always @(posedge clk or posedge rst)
    begin
      if(rst==1'b1)
        q<=5'b0;
      else if(en)
        q<=q+1'b1; 
    end
  endmodule

  module COUNTER27
 (
   input clk,rst_n,en,
   output reg[20:0] q
   );

wire rst=~rst_n;

always @(posedge clk or posedge rst)
  begin
    if(rst==1'b1)
     begin
      q <= 21'h0;
     end
    else if(en)
     begin
      q <= q+1'b1; 
      end 
  end
 endmodule

module COUNTER10_3
 (
   input clk,rst_n,en,
   output reg[1:0] q,
   output reg co
   );

wire rst=~rst_n;

always @(posedge clk or posedge rst)
  begin
    if(rst==1'b1)
     begin
      q <= 2'b0;
     end
    else if(en)
     begin
      q <= q+1'b1; 
      co <= q==2'b11;
      end 
  end
 endmodule

 module COUNTER10_e0
 (
   input clk,rst_n,en,
   output reg[10:0] q
   );

wire rst=~rst_n;

always @(posedge clk or posedge rst)
  begin
    if(rst==1'b1)
     begin
      q <= 11'b0;
     end
    else if(en)
     begin
      q <= q+1'b1; 
      end 
  end
 endmodule

 module COUNTER10_e1
 (
   input clk,rst_n,en,
   output reg[9:0] q
   );

wire rst=~rst_n;

always @(posedge clk or posedge rst)
  begin
    if(rst==1'b1)
     begin
      q <= 10'b0;
     end
    else if(en)
     begin
      q <= q+1'b1; 
      end 
  end
 endmodule

`timescale 1ns/100ps
module tb_myCOUNTER;
 parameter N=32;
  reg refclk;
  reg rst_n;
  wire co;
  wire co_e;
  wire co_o;
  wire [N-1:0] q1,q2;
  wire [N-1:0] q;

COUNTER #(32) DUT
 (
  .refclk(refclk),
  .rst_n(rst_n),
  .co(co),
  .co_e(co_e),
  .co_o(co_o),
  .q1(q1), 
  .q2(q2),
  .q(q)
  );
 
always #5  refclk=~refclk;

initial
begin
 refclk=1'b0; rst_n=1'b0;
repeat(1000) @(posedge refclk); rst_n=1'b1;

repeat(10000) @(posedge refclk);
@(posedge refclk); rst_n=1'b0;
repeat(100) @(posedge refclk); rst_n=1'b1;


end


  endmodule

 

[견우]

refence 클럭 100MHz 에서 QDR 데이터 카운터 속도 400MHz로 동작하는 ODR 카운터