Re: Re: Re: Re: Re: 계수기

[견우]

module COUNTER
 #(parameter N=32)
 (
 (* IOB="true" *)  input refclk,
  (* IOB="true" *) input rst_n,
  (* IOB="true" *) output co,
  (* IOB="true" *) output co_e,
  (* IOB="true" *) output co_o,
  (* IOB="true" *) output wire[N-1:0] q1,
  (* IOB="true" *) output reg [N-1:0] q2,q3,q4,q5,q6,q7,
  (* IOB="true" *) output reg [N-1:0] q,
  (* IOB="true" *) output reg [N-1:0] qo
  );

  
//wire [31:0] out1,out2;
wire co_e1,co_o1;
wire co_e2;  //co_e3,co_e4;
wire co_o2;  // co_o3,co_o4;
wire clk,clk2,clk3,clk4,clk5;
wire reset = ~rst_n & locked;
reg[31:0] q9,q10,q11,q12,q13,q14,q15,q16;
reg [N-1:0] q8;
  clk_wiz_0  U00
  (
  // Clock out ports  
  .clk_out1(clk1),    //CLK62.5
  .clk_out2(clk2),   //CLK125M
  .clk_out3(clk3),   //CLK250M
  .clk_out4(clk4),   //CLK500M
  .clk_out5(clk5),   //CLK
  // Status and control signals               
  .reset(1'b0), 
  .locked(locked),
 // Clock in ports
  .clk_in1(refclk)
  );

(* dont_touch ="yes" *) reg [N-1:0] tq1;
(* dont_touch ="yes" *) reg [N-1:0] tq2;
(* dont_touch ="yes" *) reg [N-1:0] tq3;
(* dont_touch ="yes" *) reg [N-1:0] tq4;
(* dont_touch ="yes" *) reg [N-1:0] tq5;
(* dont_touch ="yes" *) reg [N-1:0] tq6;
(* dont_touch ="yes" *) reg [N-1:0] tq7;
(* dont_touch ="yes" *) reg [N-1:0] tq8;
(* dont_touch ="yes" *) reg [N-1:0] tq9;
(* dont_touch ="yes" *) reg [N-1:0] tq10;
(* dont_touch ="yes" *) reg [N-1:0] tq11;
(* dont_touch ="yes" *) reg [N-1:0] tq12;
(* dont_touch ="yes" *) reg [N-1:0] tq13;
(* dont_touch ="yes" *) reg [N-1:0] tq14;
(* dont_touch ="yes" *) reg [N-1:0] tq15;
(* dont_touch ="yes" *) reg [N-1:0] tq16;
(* dont_touch ="yes" *) reg [N-1:0] qi;
(* dont_touch ="yes" *) reg [N-1:0] qi2;
(* dont_touch ="yes" *) reg [N-1:0] qi3;
(* dont_touch ="yes" *) reg [N-1:0] qi4;
(* dont_touch ="yes" *) reg [N-1:0] qi5;
(* dont_touch ="yes" *) reg [N-1:0] qi6;
(* dont_touch ="yes" *) reg [N-1:0] qi7;
(* dont_touch ="yes" *) reg [N-1:0] qi8;
(* dont_touch ="yes" *) reg [N-1:0] qi9;
(* dont_touch ="yes" *) reg [N-1:0] qi10;
(* dont_touch ="yes" *) reg [N-1:0] qi11;
(* dont_touch ="yes" *) reg [N-1:0] qi12;
(* dont_touch ="yes" *) reg [N-1:0] qi13;
(* dont_touch ="yes" *) reg [N-1:0] qi14;
(* dont_touch ="yes" *) reg [N-1:0] qi15;

(* dont_touch ="yes" *) reg [N-1:0] tqr1;
(* dont_touch ="yes" *) reg [N-1:0] to1,to2,to3,to4,to5,to6,to7,to8;
(* dont_touch ="yes" *) wire [N-1:0] tqo,tqo1,tqo2,tqo3,tqo4,tqo5,tqo6,tqo7,tqo8;
reg [2:0]t1;
reg t0,clk1d;

(* dont_touch ="yes" *) reg  clk1_d,clk2_d,clk3_d,clk3_2d;
wire Rst_n;
initial
 begin
 
end

always @(posedge clk4)
 begin

 if(rst_n==1'b1)
 begin
  tq1[31:4]<=q1[31:4];
  tq2[31:4]<=q1[31:4];
  tq3[31:4]<=q1[31:4];
  tq4[31:4]<=q1[31:4];
  tq5[31:4]<=q1[31:4];
  tq6[31:4]<=q1[31:4];
  tq7[31:4]<=q1[31:4];
  tq8[31:4]<=q1[31:4];
  tq9[31:4]<=q1[31:4];
  tq10[31:4]<=q1[31:4];
  tq11[31:4]<=q1[31:4];
  tq12[31:4]<=q1[31:4];
  tq13[31:4]<=q1[31:4];
  tq14[31:4]<=q1[31:4];
  tq15[31:4]<=q1[31:4];
  tq16[31:4]<=q1[31:4];
/*
  tq1[3:0]<=q1[3:0];
  tq2[3:0]<=q2[3:0];
  tq3[3:0]<=q3[3:0];
  tq4[3:0]<=q4[3:0];
  tq5[3:0]<=q5[3:0];
  tq6[3:0]<=q6[3:0];
  tq7[3:0]<=q7[3:0];
  tq8[3:0]<=q8[3:0];
  tq9[3:0]<=q9[3:0];
  tq10[3:0]<=q10[3:0];
  tq11[3:0]<=q11[3:0];
  tq12[3:0]<=q12[3:0];
  tq13[3:0]<=q13[3:0];
  tq14[3:0]<=q14[3:0];
  tq15[3:0]<=q15[3:0];
  tq16[3:0]<=q16[3:0];
*/
  tq16[3:0]<=4'b1111;
  tq15[3:0]<=4'b1110;
  tq14[3:0]<=4'b1101;
  tq13[3:0]<=4'b1100;
  tq12[3:0]<=4'b1011;
  tq11[3:0]<=4'b1010;
  tq10[3:0]<=4'b1001;
  tq9[3:0]<=4'b1000;
  tq8[3:0]<=4'b0111;
  tq7[3:0]<=4'b0110;
  tq6[3:0]<=4'b0101;
  tq5[3:0]<=4'b0100;
  tq4[3:0]<=4'b0011;
  tq3[3:0]<=4'b0010;
  tq2[3:0]<=4'b0001; 
  tq1[3:0]<=q1[3:0];

   end
  else
   begin

  tq1[31:4]<=q1[31:4];
  tq2[31:4]<=q1[31:4];
  tq3[31:4]<=q1[31:4];
  tq4[31:4]<=q1[31:4];
  tq5[31:4]<=q1[31:4];
  tq6[31:4]<=q1[31:4];
  tq7[31:4]<=q1[31:4];
  tq8[31:4]<=q1[31:4];
  tq9[31:4]<=q1[31:4];
  tq10[31:4]<=q1[31:4];
  tq11[31:4]<=q1[31:4];
  tq12[31:4]<=q1[31:4];
  tq13[31:4]<=q1[31:4];
  tq14[31:4]<=q1[31:4];
  tq15[31:4]<=q1[31:4];
  tq16[31:4]<=q1[31:4];

  tq1[3:0]<=q1[3:0];
  tq2[3:0]<=q2[3:0];
  tq3[3:0]<=q3[3:0];
  tq4[3:0]<=q4[3:0];
  tq5[3:0]<=q5[3:0];
  tq6[3:0]<=q6[3:0];
  tq7[3:0]<=q7[3:0];
  tq8[3:0]<=q8[3:0];
  tq9[3:0]<=q9[3:0];
  tq10[3:0]<=q10[3:0];
  tq11[3:0]<=q11[3:0];
  tq12[3:0]<=q12[3:0];
  tq13[3:0]<=q13[3:0];
  tq14[3:0]<=q14[3:0];
  tq15[3:0]<=q15[3:0];
  tq16[3:0]<=q16[3:0];
   end

 
 
  
  clk1d<=clk1_d;
  
  q<=tq1; 
  q2<=tq2;
  q3<=tq3;
  q4<=tq4;
  q5<=tq5;
  q6<=tq6;
  q7<=tq7;
  q8<=tq8;
 /* q<=qi;
  q2<=qi2;
  q3<=qi3;
  q4<=qi4;
  q5<=qi5;
  q6<=qi6;
  q7<=qi7;
  q8<=qi8;
 */ 
  

end 

reg clk4_d;
reg clk4d;

always @(negedge clk5)
 begin
  clk4d<=~clk4;
  clk3_d<=~clk3;
  clk3_2d<=~clk3_d;
  tqr1<=tqo;
  end

always @(posedge clk5)
 begin
   clk4_d<=clk4d;
   qo <=tqo;
 end

always @(posedge clk3_d)
 begin
  clk1_d<=~clk1;
  clk2_d<=~clk2;
 end

always @(posedge clk3_d)
 begin
  to1<=tqo1;
  to2<=tqo2;
  to3<=tqo3;
  to4<=tqo4;
end
  
always @(posedge clk4_d)
 begin
  to6<=tqo6;
  to5<=tqo5;
end


generate
  genvar i;
    for(i=0; i<N; i=i+1)
      begin:genI
        LUT6 #(.INIT(64'b1111_1111_0000_0000__1111_0000_1111_0000__1100_1100_1100_1100__1010_1010_1010_1010)) L00 (.O(tqo1[i]),.I3(tq1[i]),.I2(tq5[i]),.I1(tq9[i]) ,.I0(tq13[i]),.I4(clk2),.I5(clk1));
        LUT6 #(.INIT(64'b1111_1111_0000_0000__1111_0000_1111_0000__1100_1100_1100_1100__1010_1010_1010_1010)) L01 (.O(tqo2[i]),.I3(tq2[i]),.I2(tq6[i]),.I1(tq10[i]),.I0(tq14[i]),.I4(clk2),.I5(clk1));
        LUT6 #(.INIT(64'b1111_1111_0000_0000__1111_0000_1111_0000__1100_1100_1100_1100__1010_1010_1010_1010)) L02 (.O(tqo3[i]),.I3(tq3[i]),.I2(tq7[i]),.I1(tq11[i]),.I0(tq15[i]),.I4(clk2),.I5(clk1));
        LUT6 #(.INIT(64'b1111_1111_0000_0000__1111_0000_1111_0000__1100_1100_1100_1100__1010_1010_1010_1010)) L03 (.O(tqo4[i]),.I3(tq4[i]),.I2(tq8[i]),.I1(tq12[i]),.I0(tq16[i]),.I4(clk2),.I5(clk1));
        LUT5 #(.INIT(32'b1100_1010_1100_1010__1100_1010_1100_1010)) L04 (.O(tqo5[i]),.I0(to1[i]),.I1(to3[i]),.I2(~clk3_d),.I3(clk2_d),.I4(clk1_d));
        LUT5 #(.INIT(32'b1100_1010_1100_1010__1100_1010_1100_1010)) L05 (.O(tqo6[i]),.I0(to2[i]),.I1(to4[i]),.I2(~clk3_d),.I3(clk2_d),.I4(clk1_d));
        LUT3 #(.INIT(8'b1100_1010)) L06 (.O(tqo[i]),.I0(to6[i]),.I1(to5[i]),.I2(clk4_d));
      end
 endgenerate

LUT36_p U0
 (
   .clk(clk1),
   .rst_n(Rst_n),
   .i({q1[31:2],2'b11}),
   .o(co_e2),
   .o1(co)
   );

LUT36_p U1
 (
   .clk(clk1),
   .rst_n(Rst_n),
   .i({q2[31:2],2'b11}),
   .o(co_o2),
   .o1()
   );


assign q1[3:0]=4'b0000;

assign co_e = co_e2;
assign co_o = co_o2;


wire enable = locked;
// genRST_n    RST (.clk(clk1d)  ,.rst_n(rst_n),.Rst_n(Rst_n));
genRST_n    RST (.clk(clk3_2d)  ,.rst_n(rst_n),.Rst_n(Rst_n));

COUNTER10_e  CNT1 (.clk(clk1)  ,.rst_n(Rst_n),.en(enable),.q(q1[13:4])  ,.co(co_e1));
COUNTER10_e1 CNT2 (.clk(clk1),.rst_n(Rst_n),.en(co_e1),.q(q1[23:14]));
COUNTER10_e2 CNT3 (.clk(clk1),.rst_n(Rst_n),.en(co_e2),.q(q1[31:24]));

endmodule

module LUT36_p
 (
   input clk,
   input rst_n,
   input  [31:0] i,
   output reg o,
   output reg o1
   );
wire w0,w1,w2,w3,w4,w5,w6,w60,w30;


/*
LUT6 #(.INIT(64'h8000_0000_0000_0000) L0 (.O(w0),.I0(i[0]),.I1(i[1]),.I2(i[2]),.I3(i[3]),.I4(i[4]),.I5(i[5]));
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L1 (.O(w1),.I0(i[6]),.I1(i[7]),.I2(i[8]),.I3(i[9]),.I4(i[10]),.I5(i[11]));
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L2 (.O(w2),.I0(i[12]),.I1(i[13]),.I2(i[14]),.I3(i[15]),.I4(i[16]),.I5(i[17]));
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L3 (.O(w3),.I0(i[18]),.I1(i[19]),.I2(i[20]),.I3(i[21]),.I4(i[22]),.I5(i[23]));
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L4 (.O(w4),.I0(i[24]),.I1(i[25]),.I2(i[26]),.I3(i[27]),.I4(i[28]),.I5(i[29]));
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L5 (.O(w5),.I0(i[30]),.I1(i[31]),.I2(i[32]),.I3(i[33]),.I4(i[34]),.I5(i[35]));
*/
LUT6 #(.INIT(64'h0800_0000_0000_0000)) L0 (.O(w0),.I0(i[0]),.I1(i[1]),.I2(i[2]),.I3(i[3]),.I4(i[4]),.I5(i[5]));
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L1 (.O(w1),.I0(i[6]),.I1(i[7]),.I2(i[8]),.I3(i[9]),.I4(i[10]),.I5(i[11]));
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L2 (.O(w2),.I0(i[12]),.I1(i[13]),.I2(i[14]),.I3(i[15]),.I4(i[16]),.I5(i[17]));
LUT4 #(.INIT(16'h8000)) L3 (.O(w3),.I0(i[18]),.I1(i[19]),.I2(i[20]),.I3(i[21]));
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L30 (.O(w30),.I0(i[18]),.I1(i[19]),.I2(i[20]),.I3(i[21]),.I4(i[22]),.I5(i[23]));
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L4 (.O(w4),.I0(i[24]),.I1(i[25]),.I2(i[26]),.I3(i[27]),.I4(i[28]),.I5(i[29]));
LUT2 #(.INIT(4'h4))                     L5 (.O(w5),.I0(i[30]),.I1(i[31]));
// LUT6 #(.INIT(64'h8000_0000_0000_0000)) L4 (.O(w4),.I0(i[24]),.I1(i[25]),.I2(i[26]),.I3(i[27]),.I4(i[28]),.I5(i[29]));
// LUT2 #(.INIT(4'h1)) L5 (.O(w5),.I0(i[30]),.I1(i[31]));

/*
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L0 (.O(w0),.I0(i[0]),.I1(i[1]),.I2(i[2]),.I3(i[3]),.I4(i[4]),.I5(i[5]));
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L1 (.O(w1),.I0(i[6]),.I1(i[7]),.I2(i[8]),.I3(i[9]),.I4(i[10]),.I5(i[11]));
LUT6 #(.INIT(64'h8000_0000_0000_0000)) L2 (.O(w2),.I0(i[12]),.I1(i[13]),.I2(i[14]),.I3(i[15]),.I4(i[16]),.I5(i[17]));
LUT3 #(.INIT(08'h80)) L3 (.O(w3),.I0(i[18]),.I1(i[19]),.I2(i[20]));
*/
/*
LUT6 #(.INIT(64'h2000_0000_0000_0000)) L0 (.O(w0),.I0(i[0]),.I1(i[1]),.I2(i[2]),.I3(i[3]),.I4(i[4]),.I5(i[5]));
LUT6 #(.INIT(64'h0000_0000_0000_0001)) L1 (.O(w1),.I0(i[6]),.I1(i[7]),.I2(i[8]),.I3(i[9]),.I4(i[10]),.I5(i[11]));
LUT6 #(.INIT(64'h0000_0000_0000_0001)) L2 (.O(w2),.I0(i[12]),.I1(i[13]),.I2(i[14]),.I3(i[15]),.I4(i[16]),.I5(i[17]));
LUT3 #(.INIT(08'h01)) L3 (.O(w3),.I0(i[18]),.I1(i[19]),.I2(i[20]));
*/
reg r0,r1,r2,r3,r4,r5,r30;

always @(posedge clk)
  begin
   if(rst_n==1'b0)
    begin
      r0<=1'b0;
      r1<=1'b0;
      r2<=1'b0;
      r3<=1'b0;
      r4<=1'b0;
      r5<=1'b0;
      o<=1'b0;
      o1<=1'b0;
    end
   else
    begin
      r0<=w0;
      r1<=w1;
      r2<=w2;
      r3<=w3;
      r30 <= w30;
      r4<=w4;
      r5<=w5;
      o <=w6;
      o1 <=w60;


    end
  end

// LUT6 #(.INIT(64'h1000_0000)) L6 (.O(w6),.I0(r0),.I1(r1),.I2(r2),.I3(r3),.I4(r4),.I5(r5));
LUT4 #(.INIT(16'h8000)) L6 (.O(w6),.I0(r0),.I1(r1),.I2(r2),.I3(r3));
LUT6 #(.INIT(64'h1000_0000)) L7 (.O(w60),.I0(r0),.I1(r1),.I2(r2),.I3(r30),.I4(r4),.I5(r5));

endmodule

  
 module COUNTER5_inc2_0
 (
   input clk,rst_n,en,
   output reg [4:0] q
   );
  
 
wire rst=~rst_n;
   
   always @(posedge clk or posedge rst)
    begin
      if(rst==1'b1)
        q<=5'b0;
      else if(en)
        q<=q+1'b1; 
    end
  endmodule
  
  
module COUNTER10_e
  #(parameter ADJ=5'b1_1110)
  (
   input clk,rst_n,en,
   output wire [9:0] q,
   output reg co
   );
//   reg en1,en1_1;


reg co_r;
reg en_1,en_1d;
reg rst_ns;
reg co1;

always @(*)
 begin
   en_1 <= en_1d;
   co <=co1; 
 end

COUNTER5_inc2_0 U0 (.clk(clk),.rst_n(rst_n),.en(en),.q(q[4:0])); 

always @(posedge clk)
 begin
  en_1d<= q[4:0]==5'b1_1110;
  co_r <= q[4:0]==5'b1_1111 && q[9:5]==5'b1_1111; 
  co1  <= q[4:0]==5'b1_1110 && q[9:5]==5'b1_1111; 
  rst_ns <= rst_n & ~co_r;
 end
 
 COUNTER5 U1 (.clk(clk),.rst_n(rst_ns),.en(en_1),.q(q[9:5]));

 endmodule

 
module COUNTER5
 (
   input clk,rst_n,en,
   output reg [4:0] q
   );
   
wire rst=~rst_n;
   
   always @(posedge clk or posedge rst)
    begin
      if(rst==1'b1)
        q<=5'b0;
      else if(en)
        q<=q+1'b1; 
    end
  endmodule

  module COUNTER27
 (
   input clk,rst_n,en,
   output reg[20:0] q
   );

wire rst=~rst_n;

always @(posedge clk or posedge rst)
  begin
    if(rst==1'b1)
     begin
      q <= 21'h0;
     end
    else if(en)
     begin
      q <= q+1'b1; 
      end 
  end
 endmodule

module COUNTER10_3
 (
   input clk,rst_n,en,
   output reg[1:0] q,
   output reg co
   );

wire rst=~rst_n;

always @(posedge clk or posedge rst)
  begin
    if(rst==1'b1)
     begin
      q <= 2'b0;
     end
    else if(en)
     begin
      q <= q+1'b1; 
      co <= q==2'b11;
      end 
  end
 endmodule

 module COUNTER10_e0
 (
   input clk,rst_n,en,
   output reg[10:0] q
   );

wire rst=~rst_n;

always @(posedge clk or posedge rst)
  begin
    if(rst==1'b1)
     begin
      q <= 11'b0;
     end
    else if(en)
     begin
      q <= q+1'b1; 
      end 
  end
 endmodule

 module COUNTER10_e1
 (
   input clk,rst_n,en,
   output reg[9:0] q
   );

wire rst=~rst_n;

always @(posedge clk or posedge rst)
  begin
    if(rst==1'b1)
     begin
      q <= 10'b0;
     end
    else if(en)
     begin
      q <= q+1'b1; 
      end 
  end
 endmodule

 module COUNTER10_e2
 (
   input clk,rst_n,en,
   output reg[8:0] q
   );

wire rst=~rst_n;

always @(posedge clk or posedge rst)
  begin
    if(rst==1'b1)
     begin
      q <= 9'b0;
     end
    else if(en)
     begin
      q <= q+1'b1; 
      end 
  end
 endmodule

module genRST_n  
 ( input clk,
   input rst_n,
   output reg Rst_n
 );

reg [3:0] r;
always @(posedge clk)
 begin
   r[0]<= rst_n;
   r[1]<= r[0];
   r[2]<= r[1];
   r[3]<= r[2];
   Rst_n<=r[0];
  end
endmodule

`timescale 1ns/100ps
module tb_myCOUNTER;
 parameter N=32;
  reg refclk;
  reg rst_n;
  wire co;
  wire co_e;
  wire co_o;
  wire [N-1:0] q1,q2;
  wire [N-1:0] q3,q4;
  wire [N-1:0] q5,q6;
  wire [N-1:0] q7;
  wire [N-1:0] qo,q;

COUNTER #(32) DUT
 (
  .refclk(refclk),
  .rst_n(rst_n),
  .co(co),
  .co_e(co_e),
  .co_o(co_o),
  .q1(q1), 
  .q2(q2),
  .q3(q3),
  .q4(q4),
  .q5(q5),
  .q6(q6),
  .q7(q7),
  .qo(qo),
  .q(q)
  );
 
always #5  refclk=~refclk;

initial
begin
 refclk=1'b0; rst_n=1'b0;
repeat(1000) @(posedge refclk); rst_n=1'b1;

repeat(10000) @(posedge refclk);
@(posedge refclk); rst_n=1'b0;
repeat(100) @(posedge refclk); rst_n=1'b1;


end


  endmodule

 

[견우]

리소스 쉐어링에 의해 분산형 카운터회로를 줄인 로직, 레퍼런스 클럭과 동일 주파수의 클럭에 대해서 HDR 속도를 갖는 카운터 발생
실제 카운터 로직은 동작 속도가 좀 안나온다. 하위비트 부분을 롬 코드 카운터로 하고 상위 비트들을 한개의 공유된 카운터로 부터 만들어 고속 카운터 동작에 이용한다.