`timescale 1ns/10ps
module bidirIO
#(parameter N=1)
(
inout [N-1:0] data,odata,
inout [N-1:0] rdata,
input dir, //1:in , 0: out
output parity,
input [N-1:0] iReg, // select input data
input [N-1:0] oReg, // select output data
output reg errorN
);
wire [N-1:0] data_i,odata_i;
wire [N-1:0] data_o;
wire [N-1:0] pdata;
assign #1 odata[0]= (dir==1'b1) ? data[0] : 1'bz;
assign #1 data[0]= (dir==1'b0) ? odata[0]:1'bz;
assign data_i[0]=data[0];
assign odata_i[0]=odata[0];
endmodule
`timescale 10ns/1ns
module tb_bidirIO;
parameter N=1;
wire [N-1:0] data,odata;
wire [N-1:0] rdata;
reg [N-1:0] data_io,odata_io;
reg [N-1:0] rdata_io;
reg dir; //1:in , 0: out
wire parity;
reg [N-1:0] iReg; // select input data
reg [N-1:0] oReg; // select output data
wire errorN;
bidirIO #(.N(1)) DUT
(
.data(data),.odata(odata),
.rdata(rdata),
.dir(dir), //1:in , 0: out
.parity(parity),
.iReg(iReg), // select input
.oReg(oReg), // select output data
.errorN(errorN)
);
assign data=data_io;
assign odata=odata_io;
assign rdata=rdata_io;
initial
begin
#0 data_io=4'b0; odata_io=4'bz; rdata_io=4'bz; dir=1'b1;
#100 data_io=4'bz; odata_io=4'b1111; rdata_io=4'bz; dir=1'b0;
#100;
end
endmodule