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5.19 MINOR LOOP BOARD, 1A1A13
The minor loop, Figures 5.40/41 and block diagram, Figure 5.39, generates the small (100 Hz) steps in the synthesizer, Its output, a 1.0000 to 1.0999 MHz signal, is the reference for the translator Loop and comprise the last three digits of the transceiver frequency.
The VCO, Q5, C35, C36, L9 and CR2 through CR6 is a colpitts oscillator whose frequency (10.000 to 10.999 MHz) is determined by the DC voltage at the junction of CR2 and CR3. The V output drives two isolation buffers. The first, Q6 and associated components, drives saturated amplifier 8, whose output drives U7, a divide-by-10 counter, "The minor loop output is pin 11 of U7. Inductor L3, which is in series with the output, slows the waveform transition times to limit harmonic output. The second buffer, 27 and associated components, feed saturated amplifier Q1, which drives programmable dividers U1 through U6,
The programmable divider functions in the following manner: U3, U4, U5 and U6 are parallel - loadable UP/ DOWN counters which are cascaded and permanently connected to count DOWN. Counter U6 is the most significant digit and is permanently connected to load 10 each time its load line goes low, U3 is the least significant. U2 is an array of open collector inverters which have their outputs connected together to form a NOR gate. The output (pins 2, 4, 6, 8, 10 and 12) can only go high if all the inputs (pins 1, 3, 5, 9, 11 and 13) are low. The U2 inputs are connected so that the output goes high when the counter (U6-U3) contains the number 002. To understand the operation, assume that the counter has just been loaded with the number 124. The counters begin counting down. Because the D input, pin 12, is low, pin 9 of U1 (Q) stays low and pin 8 (Q) stays high. After 20,000 pulses, U6 underflows and pin 1 (U2) goes low.
After another 100 pulses, U5 underflows and U2, pin 3, goes low. After another 20 pulses, U4 underflows and U2, pin 5, goes low. After another 2 pulses, pins 9, 11 and 13 of U2 are low, so the "output" of number 002 and the D input, pin 12 of U1 goes high (this is the programmable divider output pulse), and pin goes low, again loading U3, U4, US and U6 with the divide number. The next pulse (number 000) toggles pin 8 high and pin 9 low. The cycle can now repeat.
The output of the programmable divider (U1, pin 9) is fed to the phase/frequency detector U9, where it is compared with the l kHz reference. If the divider output is too low in frequency or lagging the 1 kHz reference in phase, the phase detector output (pin 5 and 10) goes down. This causes the voltage of the VCO control line to rise, which rises the frequency to correct the error.
The loop amplifier consists of Q2 and Q3, which for a high input impedance inverting stage. The amplifier and feedback components (R4, R5, C27 and C28) form an active loop filter which determines the overall loop stability. Transistor 04, with componets R7, R8, C29 and C30 forms and active lowpass filter with a sharp corner and steep rolloff to attenuate the reference sidebands.
Components RI0, R11 and R12 and C31, C32, C33 and C34 form a twin T-notch filter centered on 1 kHz to further. attenuate the first order sidebands.
The loss-of-lock circuitry works as follows: phase detector outputs pin 11 and pin 4 are normally high with nearly 100% duty cycle in a properly locked loop. This means that the base and, therefore, the emitter of Q9 is also high, driving pin 12 of U8 low. This makes pins 2 and 4 of U8 high so the LED is off. When the loop loses lock, the duty cycle will drop at either pin 11 or pin 4 (of U9). This discharges 053 through R31 faster than it can be recharged by R30, so the base voltage of 29 drops causing pin 12 of U8 to go high. This turns on the LED and drives the LL line low. The pin number (11 or 4) that goes low in loss-of-lock depends on whether the VCO frequency is too high or too low.
An on-card 8 volt regulator, U10, supplies the linear circuits with clean power.
Table 5.5 lists the minor loop VCO output frequency and divider input frequency information.
5.20 TRANSLATOR LOOP BOARD,
1A1A14 The translator loop board, Figures 5.42/43, provides the 55.530 to 55.6299 MHz signal for use by the major loop and provides the 54.53 Mhz second LO for the receiver/exciter. Also, refer to the block diagran, Figure 5.39.
The second L signal is generated by a colpitts configuration crystal oscillator, 26 and associated components. The crystal is a parallel resonant type and is adjusted on frequency by trimmer C61. An uncompensated crystal can be used because both the first and second signals are derived from it, so any 54.53 MHz frequency drift cancels in the transmit and receive frequency, leaving the overall frequency stability dependent only on the TCXO reference oscillator.
The output of the 54.53 MHz oscillator is split into two paths. One path goes to buffer 25, which drives mixer M. The other path goes to buffer 27, which provides the 0 dBm second L output. The output amplitude can be adjusted to 0 dBm by C64. Components L13, C39, 046 and 041 form a harmonic filter.
The translator output is the sum of the second LO (54.53 MHz) and the minor loop output (1.0000 to 1.0999 MHz). The Vco, consisting of Q1, L6, C63, C60 and associated components is a colpitts oscillator
whose frequency is varied by changing the control line voltage at TP6. A change in the DC voltage here will change the bias on varicap CR4, changing the VCO tank capacitance and thus, the VCO frequency. The output signal is split into two paths. One path goes through output level adjust C15, then to cascode amplifier 22 and 23. The cascode amplifier provides excellent reverse isolation and a -10 dBm output level through harmonic filter L3, L2 and associated capacitors. The other path from the VCO goes to buffer 24, which drives pin 8 of mixer M.. The output of the mixer (pins 3 and 4) is a 1.0000 to 1.0999 MHz signal. This signal is amplified by a 15 dB amplifier (08, 09 and associated components) and then coupled through R54 and C57 to lowpass filter L14, L16, C54, C55 and C56 to provide a 100 millivolt p-p signal at TP4. From here, the signal is amplified by high gain common emitter amplifiers Q10 and 211 to generate a 4 volt p-p waveform for the loop input to the phase/frequency detector (pin 1). The reference frequency is the 1.0000 to 1.0999 MHz signal from the minor loop and is fed to pin 3 of U1. Thus, the loop translator causes the Vco to generate a frequency which, when 54.53 MHz is subtracted by M2, is the same as the minor loop input frequency.
The output of phase detector U1, is at pins 5 and 10 and is a high impedance when the loop is locked. This output is connected to a leadlag type active loop filter consisting of Q12, Q13, R42, R41, C48, C47 and R40. The filter output goes through R43 to TP6. Diode CR7 prevents the voltage at TP6 from dropping below 4.3 volts and the VCO frequency from falling below 54.53 MHz, which would cause a false lock.
The loss-of-lock circuitry works as follows: phase detector outputs pin ll and pin 4 are normally high with nearly 100% duty cycle in a properly locked loop. This means that the base and, therefore, the emitter of Q14 is also high, driving pin 6 of U2 low. This makes pins 8 and 10 of U2 high so the LED is off. When the loop loses lock, the duty cycle will drop at either pin 11 or pin 4 (of U1). This discharges C43 through R37 faster than it can be recharged by R38, so the base voltage of 214 drops causing pin 6 of U2 to go high. This turns on the LED and drives LL line low. The pin number (11 or 4) that goes low in loss-oflock depends on whether the Vco frequency is too high or too low.
An on-card 8 volt regulator, U3, supplies the linear circuits with clean power.
5.21 MAJOR LOOP BOARD, 1A1A15
The major loop, Figures 5.44/45, provides the first local oscillator (LO) signal (59.53 MHz to 89.53 MHz) for the first mixer in the signal path. The loop itself uses a 50 kHz reference frequency and generates 10 MHz, 1 MHz, and 100 kHz steps. Smaller step sizes are possible by stepping the translator RF input to the major loop from 55.53 MHz to 55.6299 MHz. The translator loop takes 100 Hz steps over this range, which also gives the major loop output 100 Hz steps. The smaller step sizes are actually generated by the minor loop, so different step sizes are possible by changing minor Refer to the block diagram, Figure 5.39.
The VCO, Q7, is a colpitts oscillator with three switched ranges. The VCO control line is the junction of varicaps CR7 and CRS driven through decoupling choke, 14. The oscillator covers 59.53 MHz to 89.53 MHz in three course ranges (see Table 5.6). This keeps the loop gain expression Kvkp/N * nearly constant which insures that loop dynamics (stability, settling time) are constant throughout the range. Range switching is accomplished by PIN diodes CR13 and CR2. The top range has only varicaps CR7 and CR8 in combination with L3 determining the VCO frequency. In the middle range, CR2 is turned on, which puts C71 and C73 in parallel with the varicaps. In the low range, CR2 remains on and CR13 turned on, which adds parallel capacitors C72 and C74 to the tank circuit, Diodes CR4, CR5 and CR6 limit the oscillation amplitude. Resistor R23 sets the static FET operating point an unbypassed resistor R13 degenerates the gain slightly to limit high order harmonic production.
The output of Q6 is taken from 3:1 broadband transformer L1 (L7 and 18 are similar transformers) and fed to two additional buffers. Cascode anplifiers Q12 and Q11 provide extremely good reverse isolation (70 to 80 dB) and feeds mixer M1.
The first LO output is from buffer Q1. Components L9, L10, C42, C43 and C77 provide harmonic filtering. R52 is used to adjust the output level.
The translator loop frequency is fed to pin l of mixer Ml and the VCO is fed to pin 8. The output, on pins 3 and 4, is amplified by Q9 and Q10 and fed to a bandpass filter consisting of L5, L6 and associated capacitors. The filter passes the difference frequency of 4 to 33.9 MHz to be further amplified by Q13 and Q14. Both the Sum Evco + E trans and difference Evco - E trans are present in the mixer output. We want only the difference frequency. The output is Fed to the clock input of U8, which is a D flip-flop connected to toggle (-2). Resistors R44 and R48 bias U8's clock input at threshold for reliable triggering. The presence of the -2 is compensated for by using a 50 kHz (not 100 kHz) reference signal for the loop.
The programmable divider determines the VCO frequency in the following manner: the output of the programmable divider (U8, pin 9) is always 50 kHz if the loop is locked. The input frequency (U8, pin 11), then, is N X 50 kHz, when N is the programmed divide number. Working back up to the VCO: (N x 50 kHz x 2) + E trans = E vco.
The programmable divider functions in the following manner: U5, U6 and U7 are parallel - loadable UP/DOWN counters which are cascaded and permanently connected to count DOWN. Counter U5 is the most significant digit, U7 the least significant. U4 is an array of open collector inverters which have their outputs connected together to form a NOR gate. The output (pins 4, 6, 8, 10 and 12) can only go high if all the inputs (pins 3, 5, 9, 11 and 13) are low. The U4 inputs are connected so that the output goes high when the counter (U5-U7) contains the number 002. To understand the operation, assume that the counter has just been loaded with the number 124. The counters begin counting down. Because of the D input, pin 12, is low, pin 9 of U8 (Q) stays low and pin 8 (Q) stays high. After 100 pulses, U5 underflows and U4, pin 3, goes low. After another 20 pulses, U6 underflows and U4, pin 5, goes low. After another 2 pulses, pins 9, 11 and 13 of us are low, so the "output" of U4, pins 4, 6, 8, 10 and 12 can go high. The counter now contains the number 002 and the D input, pin 12 of U8 goes high (this is the programmable divider output pulse), and pin goes low, again loading U5, U6 and U7 with the divide number. The next pulse (number 000) toggles pin 8 high and pin 9 low. The cycle can now repeat.
The output of the programmable divider (U8, pin 9) is fed to the phase/frequency detector U2, where it is compared with the 50 kHz reference. If the divider output is too low in frequency or lagging the 50 kHz reference in phase, the phase detector output (pins 5 and 10) goes down. This causes the voltage of the VCO control line to rise, which raises the frequency to correct the error.
The loop amplifier consists of Q5, Q4 and Q3, which form a high input impedance inverting stage. The amplifier and feedback components (C7, R12, R11 and C8 form an active loop filter, which determines the overall loop stability. Transistor Q2, with components RI0, R58, C12 and C66 forms an active lowpass filter with a sharp corner and steep rolloff to attenuate the reference sidebands. The amplifier and active lowpass are fed +24 volts from the reference board. The +24 volts is needed to increase the varicap range.
The loss-of-lock circuitry works as follows: phase detector outputs pin ll and pin 4 are normally high with nearly 100% duty cycle in a properly locked loop. This means that the base and, therefore, the emitter of Q8 is also high, driving pin 4 of U3 low. This makes pins 2 and 6 of U3 high so the LED is off. When the loop loses lock, the duty cycle will drop at either pin 11 or 4 (of U2). This discharges C25 through R32 faster than it can be recharged by R25, so the base voltage of Q8 drops causing pin 4 of U3 to go high. This turns on the LED and drives the LL line low. The pin number (11 or 4) that goes low in loss-of-lock de pends on whether the VCO frequency is too high or too low.
An on-card 8 volt regulator, U1, supplies the linear circuits with clean power.
*While a complete discussion of loop theory is beyond the scope of this technical description, the following is an extremely simplified explanation: the loop response time and setting time depends on the time constants of the loop filter components and the loop "gain" KvKp/N, where Kv is the VCO transfer constant in Radians/Sec/Volt, kp is the phase detector constant in Volts/Radian, and N is the programmable divide number. Typical numbers for the major loop might be:
Kv = 3.14 x 106
Kp = .44 so KyKp/N = 11.1 x 10^3
N = 124
Table 5.6 lists
the major loop VCO output frequency and divider program information.
5.22 FRONT PANEL, 1 A2
5.22.1 GENERAL
The front panel, Figures 5.47/48, contains all switches and controls for transceiver operation. The microphone connector, 1A2J34, auxillary connector, 1A2J35, meter, and speaker Switch are all located on the front panel. Part of the front panel assembly includes the front panel PC board assembly, 1A2AL, which contains the frequency display and associated circuitry. The front panel is pluggable to the transceiver mother board via connectors 1A2J28 and 1A2P17 and ribbon cable. Refer to Figure 5.49 for Resistor Board A, Resistor Board B and the Meter Mount Board.
5.22.2 DETAILED DESCRIPTION
The front panel contains all switches needed for the transceiver. It also provides LED indicators to show status of the transceiver, a meter to indicate transmit power or receive signal level, a phone jack and speaker for receiver audio monitoring, a key and microphone connector for transmitter keying and an audio input.
S7 is the emission mode switch. It provides mode information in BCD form. For AME operation, S7 generates the number 1. A complete table of numbers (BCD coves) generated by S7, appears on the schematic diagram, Figure 5.44. It is not active in the channelized operate mode of operation.
S8 is a channel switch. It provides BCD output for channels l through 10. The transceiver is in the channelized mode when 58 is in positions 1 through 10. Position 11 of S8 is used to generate a special code (1011), BCD, number 11, for manual mode identification. Switches S9 through S14 are connected to the display digit select output on the front panel board, so that the digit being displayed can be changed directly through UP/DOWN switches during the frequency change routine controlled by the software. The three digits on the right (10 kHz's, 1 kHz's and 100 Hz's) can also be changed indirectly by the digit next to it as a result of carry or borrow during a frequency change. Switches S9 through S14 are active only in the manual mode of operation and are active in the channelized load mode of operation only under software control.
S3 and/or S4 which are located behind the front panel, generates an interrupt signal for the microprocessor to guide the program to the load memory subroutine, and to load the TX or RX frequency and mode information from the channel selected by the CHAN/FREQ Switch S8 into the static RAM.
S17 generates a command for the coupler to perform the tuning procedure.
S6 turns the noise blanker on and off.
S1 selects the meter to indicate transmit forward power, or transmit reflected power. Transmit reflected power will be indicated only if the automatic antenna coupler is used, as the voltage for this indication is supplied by the antenna coupler.
R1 controls the base voltage of dimmer transistor Q17, on the front panel board to control the brightness of the display and indicators.
5.23 FRONT PANEL BOARD, 1A2A1
5.23.1 GENERAL
This board, Figures 5.46 and 5.47, receives signals from the logic board to display channel, frequency and emission modes. A dimmer circuit is provided to control the brightness of display through a dimmer pot on the front panel. Logic gates on this board will generate +5 volts to BCD mode switch through the control of LOAD/OPERATE switch. LOAD/ENABLE Switch, MANUAL/ENABLE switch and CHANNEL switch. It also provides display digit select signal to UP/DOWN switches on the front panel to generate T0 and T1 command during frequency change routine.
5.23.2 DETAILED DESCRIPTION
U4 receives BCD frequency and channel data from the microprocessor and converts it into a seven segment display signal to drive segment drivers Q18 through Q24.
A display code signal from the microprocessor is applied to U3, pins 1, 2, and 3. U3 decodes this signal and drives one of eight digit drivers to turn on one display digit at a time. The repetition rate of the display signal is approximately 300 Hz. U2 is an inverter driver which provides enough current to drive digit driver pairs Q1, Q9, Q2, Q10, etc., to be able to sink 700 mA peak current. Output of U2 is also sent to the front panel UP/DOWN switch ON.
Q17 and associated circuitry is used to vary the anode voltage to the displays to change their brightness.
U6 and U7 serve as logic gates to switch on and off the +5 volts to the BCD mode switch on the front panel.
The dimmer output voltage is also fed to the front panel through P27-2 for the LED indicators.
U5 is used as a switch to turn off the channel display during the manual mode of operation.
5.24 REAR PANEL ASSEMBLY, 1A3
The rear panel, Figure 5.55, contains the power input, antenna, 600 ohm audio, and accessory connector. The DC power contactor, power amplifier assembly, 1A3A1, connector board, 1A3A2, and fuses are also located on the rear panel assembly. The rear panel is pluggable to the transceiver mother board via connectors P20, P24 and P25.
As the rear panel assembly serves to provide an interconnection function between the rear panel connectors and the chassis/mother board assembly, 1A1, maintenance on this assembly is normally not required.
Should removal from the transceiver be required, the four mounting screws (two on each side) should be removed (also remove the one screw from the bottom cover), and the rear panel is easily detachable as a unit.
CAUTION
Remove all power from the transceiver before attempting to remove the rear panel assembly.
A connector board, Figures 5.51 and 5.52, serves to provide an interconnection function between the audio connector, 143-J21, the accessory connector, 1A3-J22, and the mother board, 1A1A1A1. Most of the rear panel RF bypass capacitors are mounted on this PC assembly.
5.25 125 WATT POWER AMPLIFIER ASSEMBLY, 1A3A1
5.25.1 GENERAL
The all solid state power amplifier, Figures 5.57/58 (24 volts), and Figures 5.59/60 (12 volts), accepts the +13 dBm RF drive input from the mixer assembly, 1A1A5, and provides a nominal 38 dB gain to produce 125 watts output to the antenna (through the low pass filters) in the transmit mode. Receive/transmit signal paths are controlled by relay K1, to route the antenna input directly to the high pass filter, 1A1A4, in the receive mode. Also contained on this board are circuits that sense PA over voltage, over current and over temperature. These voltages are fed to the half octave filter board, 1A1A2, which, via feedback to the transmit modulator board, 1A1A3, controls overall transmitter gain, and power output. Contained also in this module is a +13,2 VDC regulator (+24 volt module only) that supplies regulated +13 VDC to the following boards: 1A1A2, 1A1A4, 1A1A6, 1A1A8, 1A1A11, 1A1A12, 1A1A14, 1A1A15 and to the rear panel 1A3-J2l and 1A3J22,
5.25.2 DETAILED DESCRIPTION
The RF signal is fed into P1. R49, R50 and R51 form a 2 dB 50 ohm attenuator. Therefore, input signals are reduced in amplitude before reaching the first amplifier stage. Ti, Q5 and T2 serve as a +15 dB power amplifier. Two signals of equal amplitude and phase are taken from T2, to drive a push-pull power amplifier pair, Q6 and Q7. Bias voltage for 5 is established by the voltage drop across R37 and diode CR3. Output from Q6 and Q7, the second stage, is taken from T3 to drive the final push-pull output stage, Q8 and Q9, to the 125 watt output level. Bias voltage for the driver, and the power output stage is obtained from 13.2 volt regualtor via R45 and R46 to diodes CR7 and CR9. Pots R44 and R47 provide a means to adjust the operating points of the driver, and output stage for best linearity to reduce internodulation distortion. Diodes CR7 and CR9 are mounted on the heatsink to provide temperature compensation.
T4 transforms the low output impedance of Q8 and Q9 to 50 ohms, The secondary winding of T4 contains two windings of 2 1/2 turns each, connected in parallel in the group 001 amplifier and a single secondary winding of four turns in the group 002 amplifier. C49, the capacitor in parallel with the primary of T4, and capacitor C28 compensate for leakage inductance in T4 and provide high frequency condensation. R14, R13 and C33 provide feedback for Q5, and reduce gain at the low frequency end. R58 and R59 provide negative feedback from a 2 turn winding on T4 to the bases of Q8 and Q9 (24V model only).
Q3 and Q4 form a differential amplifier to provide DC over current protection. The voltage drop across R6 is applied to 04. When current through R6 reaches a value established by the adjustment of R16, a voltage appears at E5. This voltage, when fed to the half octave filter board, 1A1A2, is used to reduce drive to the amplifier.
Q1 and Q2 comprise a 13.2 volt regulator (24 VDC model only). The output voltage is set by the adjustment of R2. The output current of the voltage regulator is limited to approximately 2.0 amps. When the voltage across R53 begins to exceed 1.4 volts, diodes CR4, CR5 and CR6 begin to conduct, thereby limiting drive to Q2 and limiting the 13.2 volts output current. Diode CR8, capacitors C22 and C30, resistors R33 and R34 are the over voltage detector. Any voltage change on the collector of Q9 is fed to the transceiver or exciter, and when excessive, drive to the amplifier is reduced.
5.25.4 PA ADJUSTMENTS
Normally, adjustments to the solid state power amplifier are not required. If a component replacement or operation indicates a need for adjustments, the following adjustments can be made.
5.25.4.1 Test Set-Up
Terminate the transceiver output, 1A3-J31, in a 50 ohm, 125 watt load. Install a thru-line wattmeter (bird) or equivalent) in series with the output for these adjustments. Remove the four screws that attach the amplifier module to the rear panel assembly. Carefully position the PA module in a flat position on the test bench. Insure that all wires and harnesses are attached to the transceiver (Refer to RF pattern diagram) and that no electrical short circuit of the exposed PA module circuit board or wiring can to the chassis or other metal objects. The transceiver power amplifier assembly can be safely operated in this position for short periods.
5.25.4.2 13.2 VDC Regulator Adjust (24 Volt Model Only)
Set the transceiver frequency to 5.2 MHz, the mode to USB. Key the transceiver using the microphone PTT, but DO NOT speak into the microphone. Using a DC voltmeter connected between El and GND, adjust R2 for +13.2 VDC at El. Unkey the transceiver.
5.25.4.3 Output Stage Bias Adjust
Remove the jumper strap between El8 and E19. Connect a DC ammeter + to E18 - to E19. Using the same transceiver setting as above, key the transceiver (no modulation) adjust R47 for the 24 volt PA to 0.15A and for the 12 volt PA to 0.5A. Unkey the transceiver and turn off the power. Replace the strap between E18 and E19.
5.25.4.4 Driver Stage Bias Adjust
The transceiver settings are the same as 5.25.4.2, above. Connect an oscilloscope across the 50 ohm load. Connect the audio combiner key box described in the diagram below, apply two equal audio tones, 700 and 2300 Hz, and key the transmitter. The RF output pattern on the scope should depict the standard two-tone pattern (similar to an AM modulation pattern with 100% modulation). Adjust R44 until the area between peaks just touches the reference line.
5.25.5 Over Current Adjustment
Change the transceiver frequency to 29.999 MHz, the mode to CW and key the transceiver. 125 watts should be indicated on the wattmeter. Adjust R16, the over current adjust, until the output power starts to de-- crease. Slowly adjust R46 until full power returns. Leave R46 ad-. justed to this setting. Remove power from the transceiver, Reinstall the PA module on the rear panel assembly.
SECTION 6
OPTIONS AND ACCESSORIES
6.1 POWER AMPLIFIER FAN OPTION
The Power Amplifier (PA) option is required whenever FSK (RTTY) data is transmitted for an extended period of time. The fan is installed on the rear panel, 1A3, over the PA heaksink, 1A3Al, utilizing the four (4) mounting screws that are used to secure the power amplifier module to the rear panel. Electrical connections to the fan are made via a wiring harness and plug to mating connector 1A3-J30, in the rear panel.
6.1.1 TECHNICAL CHARACTERISTICS
6.1.1.1 Operating Voltage
+11.2 to +14 VDC, and +22.4 to +29 VDC
6.1.1.2 Fan Type
Brushless DC, 12 VDC, 4W nominal, 41 CFM air flow
6.1.1.3 Fan Control
ON/OFF
6.1.1.4 Temperature Sense Element
Remote sense thermistor (part of PA assembly)
6.1.1.5 Temperature Sense Adjust
Range 1 to 4 VDC, +15%
6.1.2 TECHNICAL DESCRIPTION
The PA fan option is designed to provide additional cooling to the PA
information supplied by a thermistor mounted on the PA heatsink (part of PA assembly). The circuit automatically supplies the proper operating voltage for the fan (12 VDC) on the 12 or 24 VDC transceiver. Refer to Figures 6.1 and 6.2.
The fan operates automatically when the PA heatsink temperature rises to approximately 60°C (140°F). The heart of the circuit is U1, an LM339 quad comparator, which is powered by U2, a monolithic 8 volt regulator. U2 always produces an 8 volt output with input voltages from 10 to 30 volts. Comparator U1A determines the switching temperature by comparing the voltage from the remote thermistor which is applied via R1 to U1, pin 4, to the "temperature threshold set" voltage applied to U1, pin 5. When the voltage on U1, pin 4, becomes greater than the voltage on U1, pin 5, ULA switches and the output voltage on U1, pin 2, becomes low, which reduces via CR3, R5 and R6, the "temperature threshold set" voltage applied to U1, pin 5. This provides a hysteresis, which prevents the circuit from reverting to its original condition until the PA heatsink temperature decreases (voltage applied to E3 increases).
U1B is connected as an inverter for the output of U1A, and drives transistors Q1 and Q2, which is used as a switch connected in series with the fan motor. Resistors R8 and R9 form a voltage divider to supply +4 volts to UIB, U1C, and UID. U1C provides a l second delay following transceiver power on, inhibiting fan operation during this time. This delay allows voltage transients to dissipate so that the correct DC input voltage range switching decision can be made before power is applied to the fan.
This decision is made by U1D, by comparing a sample of the DC input voltage applied to pin 8 via R13, to the +4 volt reference applied to pin 9. The input voltage must be greater than +17 volts before the output of U1D, pin 14, will go low. With less than +17 volts DC input at E1, the output of U1D is high. This causes Q3 to conduct, thereby causing Q4 to conduct, which applies the full input voltage at E1 to be applied to the fan.
If the DC voltage at E1 is greater than approximately +17 volts, the output of U1D goes low, turning off Q3 and Q4. This, in turn, places R18 in series with the fan, effectively supplying the correct operating voltage to the fan.
6.1.3 INSTALLATION, OPERATION, AND ADJUSTMENT
Installation of the PA fan assembly consists of mounting the assembly on the PA heatsink utilizing the four (4) mounting screws that secure the PA module to the rear panel assembly, 1A3. Remove all power to the transceiver before attempting to mount the fan assembly. Remove the four screws that secure the PA heatsink to the rear panel. Mount the fan assembly per Figure 6.3, using the same bardware Engage the connector plug from the Fan assembly into accessory connector 1A3-J30. Lock into place by twisting the outer locking ring.
An adjustiment is required on the Half Octave Filter board, 1A1A2. Remove the top cover and shield from the transceiver.
Adjust R18 on the Half octave Filter Board, 1A1A2, fully clockwise. Replace cover and shield. Adjust R3 fully counterclockwise. (Accessible through a hole in housing-reference, Figure 6.3.)
To verify proper fan operation, the transmitter must be keyed into a 50 ohm load (CW mode) at 26 MHz, After transmitting for 30 seconds, adjust R3 on the Fan Assembly clockwise until the fan operates. Use caution, as 'the heatsink can cause burns.
If it is desired to change the temperature threshold of Fan operation due to abnormal circumstances, R3 may be adjusted clockwise to increase the threshold and counterclockwise to decrease it.
Once installed, fan operation is automatic. When the PA heatsink temperature rises to approximately 60°C, the fan will operate, increasing air circulation around the PA heatsink, thereby lowering the heatsink temperature. When the heatsink temperature has been lowered to a point below that originally required for fan activation, fan operation ceases.
6.2 REMOTE OPTION
6.2.1 GENERAL
The transceiver may be supplied with a factory installed Remote Option P/N 600219-700. For more detailed information, refer to the MSR 6400 Manual, Publication No. 600250823-001.
6.2.1 REMOTE CONTROL INTERFACE BOARD, 2A1A3
This PC Board Assembly is installed within the remote controlled transceiver, and is mounted on the front panel assembly, 1A2, between the front panel board, 1A2A1, and the logic board, 1A1A9. (Refer to Figure 6.6.) Contained on this board are circuits which allow signals to and from the logic board, 1A1A9, to be routed to the transceiver front panel, or to the remote control unit. This allows frequency, channel, and mode data to the transceiver to be from the local or remote source. The assembly drawing and schematic diagram are shown in Figures 6.4 and 6.5. Circuit operation is as follows.
U1 is a tri-state buffer that is enabled in local mode operation of the transceiver, so that channel and mode data can be sent from the transceiver front panel, 1A2, through U1, to the logic board, 1A1A9. When in remote operation, (transceiver mode switch is in position 8) U1 is inhibited, and its output impedance is high.
U2 and U12 are tri-state output four bit receivers, which receive channel and mode data from the remote control unit. when U1 is inhibited, and at the end of a display period, U2 and U12 will be enabled and will transfer channel and mode data from the remote unit, 2A1, to the logic board, 1A1A9.
U4 is a dual four bit tri-state buffer, with opposite enable polarity. It is used to combine the four bit mode and frequency display information. During the frequency display cycle, pin 14 of line decoder U5 is high. Output pins 3, 5, 7, and 9 of buffer 14 are enabled, connecting frequency display data FD1, FD2, FD4, and FD8 to the inputs of U3, pins 2, 4, 6, and 8. At the end of the frequency display cycle, U5, pins 14 will go low, enabling U4 outputs, pins 18, 16, 14, and 12, which then transfers mode display data MD1, MD2, MD4, and MD8 to U3, pins 2, 4, 6, and 8.
U3 is an eight bit tri-state buffer used to combine display data and the display code, for the remote display of frequency and mode. Input pins 2, 4, 6, and 8 are for frequency display data, and pins 17, 15, and 13 are inputs for the three bit display code. U3 is enabled in the remote control mode of the transceiver, and during a display cycle. At the end of a display cycle, all display data bits (FD1, FD2, FD4, and FD8) are high, thereby back biasing diodes CRI, CR2, CR3, and CR4. This causes NAND gates U6A, U6B, and U6C to inhibit U3, (logic "1" on pins 1 and 19) and to enable U2 and U12 (logic "1" on pin 12).
The seven bit data channel of the remote control system is therefore bi-directional. During the display cycle, the data direction is from the logic board, 1A1A9, to the remote control. At the end of the display cycle, for approximately 1.5 milliseconds. The data direction is from the remote control to the logic board, 1A1A9. This is controlled by diodes CRI, CR2, CR3, and CR4, and NAND gates U6A, U6B, and U6C. During a display, at least one of the diodes (cathode) will be low, causing U6A, U6B, and U6C to enable U3, and inhibit U2 and U12. Data direction is now from the transceiver to the remote control unit. This cycle repeats approximately 300 times per second.
U9 is a DC amplifier to amplify the "FORWARD POWER" indication signal from the transceiver to 3.5 volts maximum.
The output of 19 is applied to U10, an analog switch, that is turned on by U8A during transmit. The "FOR WARD POWER" signal, "PFD” is then sent to the remote unit for application to the TX LED circuit. When U10 is enabled, U is inhibited, the "PFD” signal therefore cannot be applied to the logic board, 1A1A9, in conjunction with the frequency down signal TI, which shares the same interface line with the "PFD" signal.
Q1, Q2, and Q3 are used to detect and convert REMOTE, PTT, TUNE, and NOISE BLANKER commands to compatible
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