가위바위보 코드를 짜 봤는데요... 에러를 못찾겠어요..ㅜㅡㅠ

[SystemVerilog]

코드 올립니다.

module auto_toss

 (

   input clk,

   input reset_n,

   input gawi_a,bawi_a,bo_a,

   output draw,winA,winC

 );

wire [7:0]q;
wire [3:0] rs ;
reg  gawi_b,bawi_b,bo_b;
wire [1:0] gawi = {gawi_a,gawi_b};   // User , Computer or Random Gawi,Bawi,Bo
wire [1:0] bawi = {bawi_a,bawi_b};
wire [1:0] bo   = {bo_a,bo_b};

toss U1 (clk,gawi,bawi,bo,draw,winA,winC );

r_num U2(rs,clk,reset_n,ena,up);
   defparam U2.size = 4;

always @(negedge clk)

begin

 gawi_b = (rs[2:0]==3'b01)||(rs[2:0]==3'b100);

 bawi_b = (rs[2:0]==3'b10)||(rs[2:0]==3'b101);

 bo_b    = (rs[2:0]==3'b11)||(rs[2:0]==3'b110);

end

 
endmodule   

module toss
 (
   input clk,
   input [1:0] gawi,bawi,bo,
   output draw,
   output winA,winB
 );

wire win_a = (gawi[0] & bo[1]) | (bawi[0] & gawi[1]) | (bo[0] & bawi[1]);
wire win_b = (gawi[1] & bo[0]) | (bawi[1] & gawi[0]) | (bo[1] & bawi[0]);
assign draw =  (gawi[0] & gawi[1]) | (bawi[0] & bawi[1]) | (bo[0] & bo[1])|(rs[2:0]==3'b110)|(rs[2:0]==3'b000);;

assign winA = win_a;
assign winB = win_b;

endmodule

`timescale 1ns/100ps

module r_num
  #(parameter size=4)
 (
   output reg [size-1:0] out,
   input bit clk,rst,ena,up
   );
bit [3:0] a;  
wire [3:0]na=~a;
wire [3:0]n[15:0];
wire [3:0]m[24*16-1:0];
reg [1:0] ca;
reg [7:0] ra;
// bit clk,rst,ena,up;
bit clk1;

// always #(24*16*20) a=a+1;

  gray_sync_r16_rst U1(clk1, rst, ena,up,a);
  defparam U1.SIZE = 4 ;
 
/*
initial
 begin
 #0 clk='b0; rst='b0; ena='b0 ; up='b1; ra='0; ca='0;
 #200 rst='1; ena='b1;  
 end

 
always #20
 begin
   if(ra!=(24*16-1))
     begin
     ra=ra+1;
     if(ra==(24*8))
       clk=~clk;
     end
   else
     begin
     ra=0;       
     ca=ca+1;
     end
   out = m[ra];
 end
 */

always @(posedge clk)
  begin
   if(!rst)
     ra=0;
   else if(ra!=(24*16-1))
    begin
     ra=ra+1;
     if(ra==(24*8))
       clk1=~clk1;
    end
   else
    begin
       ra=0;       
     ca=ca+1;
    end
     out = m[ra];
  end

assign n[0]={a[3],a[2],a[1],a[0]};
assign n[1]={a[3],a[2],a[1],na[0]};
assign n[10]={a[3],a[2],na[1],a[0]};  
assign n[2]={a[3],a[2],na[1],na[0]};
assign n[7]={a[3],na[2],a[1],a[0]};
assign n[4]={a[3],na[2],a[1],na[0]};
assign n[13]={a[3],na[2],na[1],a[0]};
assign n[11]={a[3],na[2],na[1],na[0]};

assign n[3]={na[3],a[2],a[1],a[0]};
assign n[5]={na[3],a[2],a[1],na[0]};
assign n[15]={na[3],a[2],na[1],a[0]};
assign n[8]={na[3],a[2],na[1],na[0]};
assign n[14]={na[3],na[2],a[1],a[0]};
assign n[12]={na[3],na[2],a[1],na[0]};
assign n[6]={na[3],na[2],na[1],a[0]};
assign n[9]={na[3],na[2],na[1],na[0]};

generate
 genvar k;
   for( k=0; k<16;k=k+1)
    begin:genK
      assign m[0*16+k]={n[k][3],n[k][2],n[k][1],n[k][0]};
      assign m[4*16+k]={n[k][3],n[k][2],n[k][0],n[k][1]};
      assign m[8*16+k]={n[k][3],n[k][1],n[k][2],n[k][0]};
    assign m[12*16+k]={n[k][3],n[k][1],n[k][0],n[k][2]};
   assign m[16*16+k]={n[k][3],n[k][0],n[k][2],n[k][1]};    
      assign m[20*16+k]={n[k][3],n[k][0],n[k][1],n[k][2]};
     
    assign m[1*16+k]={n[k][2],n[k][3],n[k][1],n[k][0]};
      assign m[5*16+k]={n[k][2],n[k][3],n[k][0],n[k][1]};     
    assign m[9*16+k]={n[k][2],n[k][1],n[k][0],n[k][3]};
    assign m[13*16+k]={n[k][2],n[k][1],n[k][3],n[k][0]};
      assign m[17*16+k]={n[k][2],n[k][0],n[k][1],n[k][3]};    
      assign m[21*16+k]={n[k][2],n[k][0],n[k][3],n[k][1]};   
     
   assign m[2*16+k]={n[k][1],n[k][3],n[k][2],n[k][0]};
   assign m[6*16+k]={n[k][1],n[k][3],n[k][0],n[k][2]};
      assign m[10*16+k]={n[k][1],n[k][2],n[k][0],n[k][3]};
   assign m[14*16+k]={n[k][1],n[k][2],n[k][3],n[k][0]};
      assign m[18*16+k]={n[k][1],n[k][0],n[k][3],n[k][2]};
      assign m[22*16+k]={n[k][1],n[k][0],n[k][2],n[k][3]};

   assign m[3*16+k]={n[k][0],n[k][3],n[k][2],n[k][1]};
      assign m[7*16+k]={n[k][0],n[k][3],n[k][1],n[k][2]};    
   assign m[11*16+k]={n[k][0],n[k][2],n[k][3],n[k][1]};
    assign m[15*16+k]={n[k][0],n[k][2],n[k][1],n[k][3]};
      assign m[19*16+k]={n[k][0],n[k][1],n[k][2],n[k][3]};
   assign m[23*16+k]={n[k][0],n[k][1],n[k][3],n[k][2]};
    end 
endgenerate

endmodule

  
`timescale 1ns/100ps

module gray_async_1st_rom
#(parameter T0='b0)
 (
  input bit clk, rst_n, ena, up,
  input bit m_in, // msb_in
  output bit q,
  output bit qn
  );

localparam D=1;

reg T;

initial
 begin
   q<='0;
   T<=T0;
 end

always @(posedge clk or negedge rst_n)
// always @(posedge clk)
  begin
   if (!rst_n) begin
   q<= 0;
   T<=T0;
  end
  else if (ena) begin
  case({T,q})
        2'b00: begin {T,q} <= #D 2'b01; end
     2'b01: begin {T,q} <= #D 2'b11; end 
     2'b11: begin {T,q} <= #D 2'b10; end
     2'b10: begin {T,q} <= #D 2'b00; end
    endcase
  end
  end
 

always @(negedge clk)
  qn = #D (T^q);

endmodule

  
`timescale 1ns/100ps

module gray_async_1_rom
#(parameter T0='b0)
 (
  input bit clk, rst_n, ena, up,
  output bit q,
  output bit qn
  );

localparam D=1;

reg T;

initial
 begin
   q<= 0;
   T<=T0;
 end

always @(posedge clk or negedge rst_n)
// always @(posedge clk)
  begin
   if (!rst_n) begin
   q<= 0;
   T<=T0;
  end
  else if (ena) begin
  case({T,q})
        2'b00: begin {T,q} <= #D 2'b01; end
     2'b01: begin {T,q} <= #D 2'b11; end 
     2'b11: begin {T,q} <= #D 2'b10; end
     2'b10: begin {T,q} <= #D 2'b00; end
    endcase
   end
 end

always @(negedge clk)
    qn= #D (T ^ q);

endmodule

  
`timescale 1ns/100ps

module gray_sync_r16_rst(clk, rst, ena,up,q);
parameter SIZE = 16 ;

input bit clk, rst, ena,up;
output bit [SIZE-1:0] q;

bit [SIZE-1:0] qn;
wire c_in = ~|qn;

wire [SIZE:1] qn_1;
wire [SIZE:1] q_1;
wire [SIZE:1] en ;
wire [SIZE-2:0] zero='0;

assign #1 rst_g =  (q!={1'b1,zero}) ;
assign rst_n = rst & rst_g;
assign #1 qn[SIZE:1] = qn_1[SIZE:1];
assign #1 q[SIZE:1]  = q_1[SIZE:1];
assign  #0 en[1]=ena & qn[0];   //#1

generate
  genvar i;
 for(i=2;i<=SIZE;i++)
  begin:genEn
    assign #0 en[i]=en[i-1] & qn[i-1];  //#1
  end
endgenerate

gray_async_1st_rom  GC0 (clk, rst_n, ena,up,c_in,q[0],qn[0]);
  defparam GC0.T0=1'b0;

gray_async_1_rom #(0) GC1 [SIZE:1] (clk, rst_n, en,up,q_1,qn_1);
  // defparam GC1.T0=1'b0;

 
  // verification code
// hotak always #10 clk++;

reg [SIZE-1:0] prev_gray;
always @(posedge clk)
 begin
   prev_gray = #3 q ;
 end
 
wire [SIZE-1:0] code = (q ^ prev_gray) ;

assert property (@(posedge clk) disable iff(!rst_n|!ena) $onehot(code)); 
 
/*
   initial
    begin
     #0 clk='b0; rst='b1; ena='b0 ; up='b1;
     #30 rst='b0;
     #30 rst='b1;
     #20 ena='b1;
     
     #1000  rst='b1; ena='b0 ; up='b0;
     #30 rst='b0;
     #30 rst='b1;
     #20 ena='b1;

    end
*/

 endmodule